AI Hardware Summit 2020 | Kisaco Research

THE INDUSTRY EVENT FOR THE AI HARDWARE ECOSYSTEM

View Agenda
VIRTUAL EVENT | PDT Timezone
29 September, 2020-7 October, 2020
1000
Attendees across portfolio
100+
Leading speakers across portfolio
3
Industry Leading Summits

Why Attend

  • Luminary Keynotes: Unique perspectives from industry luminaries such as Turing Award Winner David Patterson, and venture capital pathfinder and computer hardware industry veteran, Vinod Khosla. Returning 2019 AIHW Summit luminary Lip-Bu Tan, CEO of Cadence Design Systems.
  • Innovations and Optimizations of Silicon & Systems for AI Training & Inference: Product launches & deep-dives from C-level executives in the AI Hardware industry.
  • Optimizing Machine Learning Systems: Hyperscaler perspectives on designing & engineering bleeding-edge AI systems, from hardware through software. ML system co-design and protecting compute performance gains by eliminating system-level inefficiencies.
  • Inference in Client (Edge) Computing: Applications for AI accelerators in cameras, consumer electronics, autonomous vehicles etc.
  • Preserving Developer Efficiency in the Adoption of Novel AI Hardware
  • Beyond Compute: AI’s Impact on memory, storage & networking: Innovations in HBM, on-chip memory and NVM, I/O bottlenecks, data transfer & high-speed interconnects.
  • Managing Machine Learning Models at Scale: Machine Learning hardware robustness & reprogrammability, model standardization & interoperability.
  • Financial & Industrial Analysis: New in 2020: Presentation of the results and insights from AI Hardware Summit’s first comprehensive vendor comparison report, detailing 20 vendors. VC investment and broader market trends & dynamics, benchmarking & metrics.

Networking at the virtual AI Hardware Summit

Get access to the attendee list before the show and schedule 1-2-1 meetings with attendees, speakers and sponsors throughout the conference so you don’t miss out on networking & interaction opportunities.

Upcoming Webinars

Advisory Board

Author:

Andrew Feldman

Co-Founder & CEO
Cerebras Systems

Andrew is a co-founder and CEO of Cerebras Systems, a venture-backed stealth-mode startup located in Los Altos, California. He leads a team of phenomenal people with a track record of building products that profoundly changed the largest markets in tech.
Prior to co-founding Cerebras Systems, he was co-founder and CEO of SeaMicro. SeaMicro (acquired by AMD for $355 million) was the pioneer in low power server technology. SeaMicro changed the trajectory of the server industry by inventing the high density, lower power, microserver category.
Prior to co-founding SeaMicro, he was Vice President of Marketing and Product Management at Force10 (acquired by Dell for $800 Million) Networks, and Vice President of Corporate Marketing and Corporate Development for Riverstone Networks (NASDAQ: RSTN) from inception through IPO.
Andrew holds a B.A. and MBA from Stanford University.

Author:

Lip-Bu Tan

CEO
Cadence Design Systems

Lip-Bu Tan has served as CEO of Cadence Design Systems, Inc. since January 2009 and has been a member of the Cadence Board of Directors since February 2004. He served as President of the company from 2009 to 2017. He also serves as chairman of Walden International, a venture capital firm he founded in 1987. Prior to founding Walden, Tan was Vice President at Chappell & Co. and held management positions at EDS Nuclear and ECHO Energy.

 

He is a member of The Business Council, is Chairman of the Board of SambaNova Systems, Inc, and serves on the board of directors of Hewlett Packard Enterprise Co., Schneider Electric, and Green Hills Software, as well as on the boards of the Electronic System Design Alliance (ESD Alliance) and the Global Semiconductor Association (GSA). He also serves on the Board of Trustees and the School of Engineering Dean’s Council at Carnegie Mellon University (CMU). Tan was the recipient of the 2016 GSA Morris Chang Exemplary Leadership Award.

 

Tan received a BS from Nanyang University in Singapore, an MS in nuclear engineering from the Massachusetts Institute of Technology, and an MBA from the University of San Francisco.

Author:

Rashmi Gopinath

General Partner
B Capital Group

Author:

Karl Freund

Senior Analyst, Machine Learning & HPC
Moor Insights & Strategy

Karl Freund is Moor Insights & Strategy’s consulting lead for HPC and Deep Learning. His recent experiences as the VP of Marketing at AMD and Calxeda, as well as his previous positions at Cray and IBM, positions him as a leading industry expert in these rapidly evolving industries. Karl works with investment and technology customers to help them understand the emerging Deep Learning opportunity in data centers, from competitive landscape to ecosystem to strategy.

Karl has worked directly with datacenter end users, OEMs, ODMs and the industry ecosystem, enabling him to help his clients define the appropriate business, product, and go-to-market strategies. He is also recognized expert on the subject of low-power servers and the emergence of ARM in the datacenter and has been a featured speaker at scores of investment and industry conferences on this topic.

Accomplishments during his career include:

  • Led the revived HPC initiative at AMD, targeting APUs at deep learning and other HPC workloads
  • Created an industry-wide thought leadership position for Calxeda in the ARM Server market
  • Helped forge the early relationship between HP and Calxeda leading to the surprise announcement of HP Moonshot with Calxeda in 2011
  • Built the IBM Power Server brand from 14% market share to over 50% share
  • Integrated the Tivoli brand into the IBM company’s branding and marketing organization
  • Co-Led the integration of HP and Apollo Marketing after the Boston-based desktop company’s acquisition

Karl’s background includes RISC and Mainframe servers, as well as HPC (Supercomputing). He has extensive experience as a global marketing executive at IBM where he was VP Marketing (2000-2010), Cray where he was VP Marketing (1995-1998), and HP where he was a Division Marketing Manager (1979-1995).

 

Author:

Yvonne Lutsch

Investment Principal
Bosch Ventures

Author:

Kunle Olukotun

Co-founder and Chief Technologist
SambaNova Systems

Kunle Olukotun is Cadence Design Professor of Electrical Engineering and Computer Science at Stanford University. He founded Afara Websystems, acquired by Sun in 2002. He is a Pioneer of Chip Multiprocessor Designs, Director of the Stanford Pervasive Parallelism Lab, and Co-leader of the Data Analytics for What’s Next (DAWN) research program.

In 2017 Olukotun and Chris Ré founded SambaNova Systems. SambaNova Systems has developed a disruptive next-generation computing platform to power machine learning and data analytics.

Author:

Cliff Young

Software Engineer
Google Brain

Author:

Marc Tremblay

Distinguished Engineer
Microsoft

Author:

Victoria Rege

Director of Alliances & Strategic Partnerships
Graphcore

Victoria has over a decade of experience in the semiconductor space. She currently heads up Strategic Partnerships at Graphcore, working with key customers and leading Research & Universities AI engagements. Previously she held several leadership positions at NVIDIA from global alliances, product marketing and campaigns to the founding of the GPU Technology Conference. Prior to joining NVIDIA, Victoria worked in the hedge fund space, as Executive Director for the Hedge Fund Business Operations Association. Victoria is a frequent contributor to ACM SIGGRAPH and is Immersive Chair for the SIGGRAPH 2019 Conference. She's also an active member of the Consumer Technology Association's AI Working Group.

Author:

Cheng Wang

Co-Founder & SVP, Architecture & Engineering
Flex Logix

CHENG WANG. Senior VP Engineering: Architecture, Software, Silicon. Originally from Shanghai, PRC. BSEECS, UC Berkeley. Cheng has led the architecture, silicon implementation and software development for eFPGA over two generations from 180nm-16nm and now neural inferencing. Two years as VLSI designer at Zoran. MSEE, EE PhD UCLA: designed 5 FPGA chips from 90nm to 40nm. 2013 Distinguished PhD Dissertation Award. 2014 ISSCC Lewis Winner Award for Outstanding Paper. Multiple patents at UCLA and Flex Logix.

Flex Logix’s NMAX platform excels at getting high hardware utilization at batch=1, which is critical for edge applications. Most of the new information is in the 2nd half of the slide deck.

NMAX delivers from 1 to 100+TOPS, as you need, at 10x lower cost and 3-5x lower power than existing solutions because we get 50-80% MAC utilization on tough models, meaning we need less silicon area, and we achieve it with 10x less DRAM bandwidth, meaning less DRAM cost and system power.

Author:

Rick Merritt

Staff Writer
NVIDIA

Author:

Jimmy Pike

SVP & Senior Fellow, Servers and Infrastructure Systems
Dell EMC

Jimmy D. Pike is a Senior Vice President and Senior Fellow at Dell EMC and serves as a senior system architect and technologist in the office of Dell’s Server and Infrastructure System’s CTO. In addition to his duties as an “at large” technologist, he focuses on high-performance computing, machine learning, and edge computing.

A longtime industry figure with more than 50 patents, Jimmy has served in various executive and technology roles:
• An analyst at the analyst firm of Moor Insights & Strategy
• Chief Architect of Dell’s Enterprise Solutions group and HPC lead technologist
• Chief Architect and Technologist for Dell’s Data Center group.

Jimmy has as also served in various other leadership roles at Intel, AT&T, NCR, and Harris Corporation.

Author:

Sailesh Kottapalli

Senior Fellow, Chief Architect, Datacenter Processor Architecture
Intel

Sailesh Kottapalli is an Intel Senior Fellow and the chief architect of data center processor architecture in the Silicon Engineering Group. He leads a team of architects responsible for developing the architecture of Intel® Xeon® and Intel® Atom™ server product lines as well as the overall compute solutions strategy for datacenter segment. He also leads a cross-organizations effort in driving the technology leadership on the Interconnect pillar. Kottapalli joined Intel in 1996 as a design engineer working on the first Intel® Itanium® processor, then code-named “Merced.” Subsequently, he served as lead engineer for several Intel Itanium and Intel Xeon processor evaluations, and more recently, as lead architect for a series of Intel Xeon server processors. His work in this area earned Kottapalli an Intel Achievement Award for delivering record generational performance improvements in a high-end server product. An active participant in industry and internal conferences, Kottapalli has authored or co-authored several published technical papers, delivered talks and taken part in roundtables and panel discussions. He has also been granted approximately three dozen patents in processor architecture, with additional patents pending. Kottapalli holds a bachelor’s degree in computer science from Andhra University in India and a master’s degree in computer engineering from Virginia Tech.

Speakers

 

David Patterson

Distinguished Engineer
Google

David Patterson is a UC Berkeley professor of the graduate school, a Google distinguished engineer, and the RISC-V Foundation Vice-Chair. He received his BA, MS, and PhD degrees from UCLA. His Reduced Instruction Set Computer (RISC), Redundant Array of Inexpensive Disks (RAID), and Network of Workstation projects helped lead to multibillion-dollar industries. This work led to about 40 awards for research, teaching, and service plus many papers and seven books. The best known book is Computer Architecture: A Quantitative Approach and the newest is The RISC-V Reader.

David Patterson

Distinguished Engineer
Google

David Patterson

Distinguished Engineer
Google

David Patterson is a UC Berkeley professor of the graduate school, a Google distinguished engineer, and the RISC-V Foundation Vice-Chair. He received his BA, MS, and PhD degrees from UCLA. His Reduced Instruction Set Computer (RISC), Redundant Array of Inexpensive Disks (RAID), and Network of Workstation projects helped lead to multibillion-dollar industries. This work led to about 40 awards for research, teaching, and service plus many papers and seven books. The best known book is Computer Architecture: A Quantitative Approach and the newest is The RISC-V Reader. He and his co-author John Hennessy shared the 2017 ACM A.M Turing Award.

 

Vinod Khosla

Founder
Khosla Ventures

V​inod Khosla is an entrepreneur, investor, and technology fan. He is the founder of Khosla Ventures, focused on impactful technology investments in software, AI, robotics, 3D printing, healthcare and more​.  Mr. Khosla was a co-founder of Daisy systems and founding CEO of Sun Microsystems where he pioneered open systems and commercial RISC processors. One of Mr. Khosla’s greatest passions is being a mentor to entrepreneurs, assisting entrepreneurs and helping them build technology-based businesses. ​Mr.

Vinod Khosla

Founder
Khosla Ventures

Vinod Khosla

Founder
Khosla Ventures

V​inod Khosla is an entrepreneur, investor, and technology fan. He is the founder of Khosla Ventures, focused on impactful technology investments in software, AI, robotics, 3D printing, healthcare and more​.  Mr. Khosla was a co-founder of Daisy systems and founding CEO of Sun Microsystems where he pioneered open systems and commercial RISC processors. One of Mr. Khosla’s greatest passions is being a mentor to entrepreneurs, assisting entrepreneurs and helping them build technology-based businesses. ​Mr. Khosla is driven by the desire to make positive impact through using to technology to reinvent societal infrastructure and multiply resources.  He is also passionate about Social Entrepreneurship. Vinod holds a Bachelor of Technology in Electrical Engineering from IIT, New Delhi, a Master's in Biomedical Engineering from Carnegie Mellon University and an MBA from the Stanford Graduate School of Business. 

 

Rashmi Gopinath

General Partner
B Capital Group

Rashmi Gopinath

General Partner
B Capital Group

Rashmi Gopinath

General Partner
B Capital Group
 

Andrew Feldman

Co-Founder & CEO
Cerebras Systems

Andrew is a co-founder and CEO of Cerebras Systems, a venture-backed stealth-mode startup located in Los Altos, California. He leads a team of phenomenal people with a track record of building products that profoundly changed the largest markets in tech.
Prior to co-founding Cerebras Systems, he was co-founder and CEO of SeaMicro. SeaMicro (acquired by AMD for $355 million) was the pioneer in low power server technology. SeaMicro changed the trajectory of the server industry by inventing the high density, lower power, microserver category.

Andrew Feldman

Co-Founder & CEO
Cerebras Systems

Andrew Feldman

Co-Founder & CEO
Cerebras Systems

Andrew is a co-founder and CEO of Cerebras Systems, a venture-backed stealth-mode startup located in Los Altos, California. He leads a team of phenomenal people with a track record of building products that profoundly changed the largest markets in tech.
Prior to co-founding Cerebras Systems, he was co-founder and CEO of SeaMicro. SeaMicro (acquired by AMD for $355 million) was the pioneer in low power server technology. SeaMicro changed the trajectory of the server industry by inventing the high density, lower power, microserver category.
Prior to co-founding SeaMicro, he was Vice President of Marketing and Product Management at Force10 (acquired by Dell for $800 Million) Networks, and Vice President of Corporate Marketing and Corporate Development for Riverstone Networks (NASDAQ: RSTN) from inception through IPO.
Andrew holds a B.A. and MBA from Stanford University.

 

Lip-Bu Tan

CEO
Cadence Design Systems

Lip-Bu Tan has served as CEO of Cadence Design Systems, Inc. since January 2009 and has been a member of the Cadence Board of Directors since February 2004. He served as President of the company from 2009 to 2017. He also serves as chairman of Walden International, a venture capital firm he founded in 1987. Prior to founding Walden, Tan was Vice President at Chappell & Co. and held management positions at EDS Nuclear and ECHO Energy.

 

Lip-Bu Tan

CEO
Cadence Design Systems

Lip-Bu Tan

CEO
Cadence Design Systems

Lip-Bu Tan has served as CEO of Cadence Design Systems, Inc. since January 2009 and has been a member of the Cadence Board of Directors since February 2004. He served as President of the company from 2009 to 2017. He also serves as chairman of Walden International, a venture capital firm he founded in 1987. Prior to founding Walden, Tan was Vice President at Chappell & Co. and held management positions at EDS Nuclear and ECHO Energy.

 

He is a member of The Business Council, is Chairman of the Board of SambaNova Systems, Inc, and serves on the board of directors of Hewlett Packard Enterprise Co., Schneider Electric, and Green Hills Software, as well as on the boards of the Electronic System Design Alliance (ESD Alliance) and the Global Semiconductor Association (GSA). He also serves on the Board of Trustees and the School of Engineering Dean’s Council at Carnegie Mellon University (CMU). Tan was the recipient of the 2016 GSA Morris Chang Exemplary Leadership Award.

 

Tan received a BS from Nanyang University in Singapore, an MS in nuclear engineering from the Massachusetts Institute of Technology, and an MBA from the University of San Francisco.

 

Carole-Jean Wu

Research Scientist
Facebook

Carole-Jean Wu is a Research Scientist at Facebook AI Research. Her research focuses on designing systems for at-scale execution of machine learning, such as personalized recommender systems and for mobile deployment. More generally, her research interests are in computer architecture with particular focus on energy- and memory-efficient systems. Carole-Jean chairs MLPerf Recommendation Benchmark Advisory Board and co-chairs MLPerf Inference. She received her M.A. and Ph.D. from Princeton and B.Sc. from Cornell.

Carole-Jean Wu

Research Scientist
Facebook

Carole-Jean Wu

Research Scientist
Facebook

Carole-Jean Wu is a Research Scientist at Facebook AI Research. Her research focuses on designing systems for at-scale execution of machine learning, such as personalized recommender systems and for mobile deployment. More generally, her research interests are in computer architecture with particular focus on energy- and memory-efficient systems. Carole-Jean chairs MLPerf Recommendation Benchmark Advisory Board and co-chairs MLPerf Inference. She received her M.A. and Ph.D. from Princeton and B.Sc. from Cornell. She holds tenure from ASU and is the recipient of the NSF CAREER Award, Facebook AI Infrastructure Mentorship Award, the IEEE Young Engineer of the Year Award, the Science Foundation Arizona Bisgrove Early Career Scholarship, and the Intel PhD Fellowship, among a number of Best Paper awards.

 

Cheng Wang

Co-Founder & SVP, Architecture & Engineering
Flex Logix

CHENG WANG. Senior VP Engineering: Architecture, Software, Silicon. Originally from Shanghai, PRC. BSEECS, UC Berkeley. Cheng has led the architecture, silicon implementation and software development for eFPGA over two generations from 180nm-16nm and now neural inferencing. Two years as VLSI designer at Zoran. MSEE, EE PhD UCLA: designed 5 FPGA chips from 90nm to 40nm. 2013 Distinguished PhD Dissertation Award. 2014 ISSCC Lewis Winner Award for Outstanding Paper. Multiple patents at UCLA and Flex Logix.

Cheng Wang

Co-Founder & SVP, Architecture & Engineering
Flex Logix

Cheng Wang

Co-Founder & SVP, Architecture & Engineering
Flex Logix

CHENG WANG. Senior VP Engineering: Architecture, Software, Silicon. Originally from Shanghai, PRC. BSEECS, UC Berkeley. Cheng has led the architecture, silicon implementation and software development for eFPGA over two generations from 180nm-16nm and now neural inferencing. Two years as VLSI designer at Zoran. MSEE, EE PhD UCLA: designed 5 FPGA chips from 90nm to 40nm. 2013 Distinguished PhD Dissertation Award. 2014 ISSCC Lewis Winner Award for Outstanding Paper. Multiple patents at UCLA and Flex Logix.

Flex Logix’s NMAX platform excels at getting high hardware utilization at batch=1, which is critical for edge applications. Most of the new information is in the 2nd half of the slide deck.

NMAX delivers from 1 to 100+TOPS, as you need, at 10x lower cost and 3-5x lower power than existing solutions because we get 50-80% MAC utilization on tough models, meaning we need less silicon area, and we achieve it with 10x less DRAM bandwidth, meaning less DRAM cost and system power.

 

Gayathri Radhakrishnan

Partner
Micron Ventures

Gayathri Radhakrishnan is currently part of the investment team at Micron Ventures, investing from $100M AI fund. She invests in startups that are leveraging AI/ML to solve critical problems in the areas of Manufacturing, Healthcare, Automotive and AgTech. Prior to that, she brings 20 years of multi-disciplinary experience across product management, product marketing, corporate strategy, M&A and venture investments in large Fortune 500 companies such as Dell and Corning and in startups.

Gayathri Radhakrishnan

Partner
Micron Ventures

Gayathri Radhakrishnan

Partner
Micron Ventures

Gayathri Radhakrishnan is currently part of the investment team at Micron Ventures, investing from $100M AI fund. She invests in startups that are leveraging AI/ML to solve critical problems in the areas of Manufacturing, Healthcare, Automotive and AgTech. Prior to that, she brings 20 years of multi-disciplinary experience across product management, product marketing, corporate strategy, M&A and venture investments in large Fortune 500 companies such as Dell and Corning and in startups. She has also worked as an early stage investor at Earlybird Venture Capital, a premier European venture capital fund based in Germany. She has a Masters in EE from The Ohio State University and MBA from INSEAD in France. She is also a Kauffman Fellow.

 

Karl Freund

Senior Analyst, Machine Learning & HPC
Moor Insights & Strategy

Karl Freund is Moor Insights & Strategy’s consulting lead for HPC and Deep Learning. His recent experiences as the VP of Marketing at AMD and Calxeda, as well as his previous positions at Cray and IBM, positions him as a leading industry expert in these rapidly evolving industries. Karl works with investment and technology customers to help them understand the emerging Deep Learning opportunity in data centers, from competitive landscape to ecosystem to strategy.

Karl Freund

Senior Analyst, Machine Learning & HPC
Moor Insights & Strategy

Karl Freund

Senior Analyst, Machine Learning & HPC
Moor Insights & Strategy

Karl Freund is Moor Insights & Strategy’s consulting lead for HPC and Deep Learning. His recent experiences as the VP of Marketing at AMD and Calxeda, as well as his previous positions at Cray and IBM, positions him as a leading industry expert in these rapidly evolving industries. Karl works with investment and technology customers to help them understand the emerging Deep Learning opportunity in data centers, from competitive landscape to ecosystem to strategy.

Karl has worked directly with datacenter end users, OEMs, ODMs and the industry ecosystem, enabling him to help his clients define the appropriate business, product, and go-to-market strategies. He is also recognized expert on the subject of low-power servers and the emergence of ARM in the datacenter and has been a featured speaker at scores of investment and industry conferences on this topic.

Accomplishments during his career include:

  • Led the revived HPC initiative at AMD, targeting APUs at deep learning and other HPC workloads
  • Created an industry-wide thought leadership position for Calxeda in the ARM Server market
  • Helped forge the early relationship between HP and Calxeda leading to the surprise announcement of HP Moonshot with Calxeda in 2011
  • Built the IBM Power Server brand from 14% market share to over 50% share
  • Integrated the Tivoli brand into the IBM company’s branding and marketing organization
  • Co-Led the integration of HP and Apollo Marketing after the Boston-based desktop company’s acquisition

Karl’s background includes RISC and Mainframe servers, as well as HPC (Supercomputing). He has extensive experience as a global marketing executive at IBM where he was VP Marketing (2000-2010), Cray where he was VP Marketing (1995-1998), and HP where he was a Division Marketing Manager (1979-1995).

 

 

Kunle Olukotun

Co-founder and Chief Technologist
SambaNova Systems

Kunle Olukotun is Cadence Design Professor of Electrical Engineering and Computer Science at Stanford University. He founded Afara Websystems, acquired by Sun in 2002. He is a Pioneer of Chip Multiprocessor Designs, Director of the Stanford Pervasive Parallelism Lab, and Co-leader of the Data Analytics for What’s Next (DAWN) research program.

In 2017 Olukotun and Chris Ré founded SambaNova Systems. SambaNova Systems has developed a disruptive next-generation computing platform to power machine learning and data analytics.

Kunle Olukotun

Co-founder and Chief Technologist
SambaNova Systems

Kunle Olukotun

Co-founder and Chief Technologist
SambaNova Systems

Kunle Olukotun is Cadence Design Professor of Electrical Engineering and Computer Science at Stanford University. He founded Afara Websystems, acquired by Sun in 2002. He is a Pioneer of Chip Multiprocessor Designs, Director of the Stanford Pervasive Parallelism Lab, and Co-leader of the Data Analytics for What’s Next (DAWN) research program.

In 2017 Olukotun and Chris Ré founded SambaNova Systems. SambaNova Systems has developed a disruptive next-generation computing platform to power machine learning and data analytics.

 

Yvonne Lutsch

Investment Principal
Bosch Ventures

Yvonne Lutsch

Investment Principal
Bosch Ventures

Yvonne Lutsch

Investment Principal
Bosch Ventures
 

Julien Simon

Global AI & Machine Learning Evangelist
Amazon Web Services

As the Global AI & Machine Learning Evangelist, Julien focuses on helping developers and enterprises bring their ideas to life. He frequently speaks at conferences, blogs on the AWS Blog and Medium, and runs an AI/ML podcast.

Julien Simon

Global AI & Machine Learning Evangelist
Amazon Web Services

Julien Simon

Global AI & Machine Learning Evangelist
Amazon Web Services

As the Global AI & Machine Learning Evangelist, Julien focuses on helping developers and enterprises bring their ideas to life. He frequently speaks at conferences, blogs on the AWS Blog and Medium, and runs an AI/ML podcast.

Prior to joining AWS, Julien served for 10 years as CTO/VP Engineering in top-tier web startups where he led large Software and Ops teams in charge of thousands of servers worldwide. In the process, he fought his way through a wide range of technical, business and procurement issues, which helped him gain a deep understanding of physical infrastructure, its limitations and how cloud computing can help.

Last but not least, Julien holds ten AWS certifications.

 

 

David Kanter

Inference Co-Chair
MLPerf

David Kanter

Inference Co-Chair
MLPerf

David Kanter

Inference Co-Chair
MLPerf
 

Peter Mattson

Staff Engineer
Google

Peter Mattson leads the ML Performance Measurement at Google. He co-founded and is the General Chair of MLPerf. Previously, he founded the Programming Systems and Applications Group at NVIDIA Research, was VP of software infrastructure for Stream Processors Inc (SPI), and was a managing engineer at Reservoir Labs. His research focuses on accelerating and understanding the behavior of machine learning systems by applying novel benchmarks and analysis tools. Peter holds a PhD and MS from Stanford University and a BS from the University of Washington.

Peter Mattson

Staff Engineer
Google

Peter Mattson

Staff Engineer
Google

Peter Mattson leads the ML Performance Measurement at Google. He co-founded and is the General Chair of MLPerf. Previously, he founded the Programming Systems and Applications Group at NVIDIA Research, was VP of software infrastructure for Stream Processors Inc (SPI), and was a managing engineer at Reservoir Labs. His research focuses on accelerating and understanding the behavior of machine learning systems by applying novel benchmarks and analysis tools. Peter holds a PhD and MS from Stanford University and a BS from the University of Washington.

 

Greg Diamos

Engineering Lead
Landing AI

Greg leads transformation engineering at Landing AI, focusing on building new AI engineering organizations.  He is a founding member of MLPerf. Previously he lead AI research at Baidu’s Silicon Valley AI Lab (SVAIL), where he helped develop the Deep Speech and Deep Voice systems. Before Baidu, Greg contributed to the design of compiler and microarchitecture technologies used in the Volta GPU at NVIDIA, including the invention of the SIMT independent thread scheduling system.

Greg Diamos

Engineering Lead
Landing AI

Greg Diamos

Engineering Lead
Landing AI

Greg leads transformation engineering at Landing AI, focusing on building new AI engineering organizations.  He is a founding member of MLPerf. Previously he lead AI research at Baidu’s Silicon Valley AI Lab (SVAIL), where he helped develop the Deep Speech and Deep Voice systems. Before Baidu, Greg contributed to the design of compiler and microarchitecture technologies used in the Volta GPU at NVIDIA, including the invention of the SIMT independent thread scheduling system. Greg holds a PhD from the Georgia Institute of Technology, where he led the development of the GPU-Ocelot dynamic compiler, which targeted CPUs and GPUs from the same program representation.

 

Dileep George

Co-Founder
Vicarious

Before cofounding Vicarious, Dileep was CTO of Numenta, an AI company he cofounded with Jeff Hawkins and Donna Dubinsky. Before Numenta, Dileep was a Research Fellow at the Redwood Neuroscience Institute. Dileep has authored 22 patents and several influential papers on the mathematics of brain circuits. Dileep’s research on hierarchical models of the brain earned him a PhD in Electrical Engineerings from Stanford University. He earned in MS in EE from Stanford and his BS from IIT in Bombay.

Dileep George

Co-Founder
Vicarious

Dileep George

Co-Founder
Vicarious

Before cofounding Vicarious, Dileep was CTO of Numenta, an AI company he cofounded with Jeff Hawkins and Donna Dubinsky. Before Numenta, Dileep was a Research Fellow at the Redwood Neuroscience Institute. Dileep has authored 22 patents and several influential papers on the mathematics of brain circuits. Dileep’s research on hierarchical models of the brain earned him a PhD in Electrical Engineerings from Stanford University. He earned in MS in EE from Stanford and his BS from IIT in Bombay.

 

Zaid Kahn

GM, Azure Infrastructure
Microsoft

Zaid is currently GM in the Cloud Hardware Infrastructure Engineering where he leads a team focusing on advanced architecture and engineering efforts for AI. He is passionate about building balanced teams of artists and soldiers that solve incredibly difficult problems at scale.

Zaid Kahn

GM, Azure Infrastructure
Microsoft

Zaid Kahn

GM, Azure Infrastructure
Microsoft

Zaid is currently GM in the Cloud Hardware Infrastructure Engineering where he leads a team focusing on advanced architecture and engineering efforts for AI. He is passionate about building balanced teams of artists and soldiers that solve incredibly difficult problems at scale.

Prior to Microsoft Zaid was head of infrastructure engineering at LinkedIn responsible for all aspects of engineering for Datacenters, Compute, Networking, Storage and Hardware. He also lead several software development teams spanning from BMC, network operating systems, server and network fleet automation to SDN efforts inside the datacenter and global backbone including edge. He introduced the concept of disaggregation inside LinkedIn and pioneered JDM with multiple vendors through key initiatives like OpenSwitch, Open19 essentially controlling destiny for hardware development at LinkedIn. During his 9 year tenure at LinkedIn his team scaled network and systems 150X, members from 50M to 675M, and hiring someone every 7 seconds on the LinkedIn Platform.

Prior to LinkedIn Zaid was Network Architect at WebEx responsible for building the MediaTone network and later I built a startup that built a pattern recognition security chip using NPU/FPGA. Zaid holds several patents in networking and SDN and is also a recognized industry leader. He previously served as a board member of the Open19 Foundation and San Francisco chapter of Internet Society. Currently he serves on DE-CIX and Pensando advisory boards.

 

Michael Azoff

Chief Analyst
Kisaco Research

With over 17 years analyst experience, most recently at Ovum/ Informa, Michael Azoff joined Kisaco Research, the company behind the AI Hardware and Edge AI Summit series, in 2020 as Chief Analyst. 

Michael Azoff

Chief Analyst
Kisaco Research

Michael Azoff

Chief Analyst
Kisaco Research

With over 17 years analyst experience, most recently at Ovum/ Informa, Michael Azoff joined Kisaco Research, the company behind the AI Hardware and Edge AI Summit series, in 2020 as Chief Analyst. 

Eitan Michael Azoff, PhD, MSc, BEng.

HQ’d in Kisaco Research’s London office, Michael's current focus is launching Kisaco Research vendor product comparison reports with the new Kisaco Leadership Chart (KLC) analyst chart. The first KLC is also the first analyst chart in the AI chip industry, with 16 vendors having participated in the research.

In his career Michael worked at Rutherford Appleton Laboratory building simulators for electron and hole transport in semiconductors for UK national and European community research projects and published papers in learned journals. He then turned to building neural networks when KR Analysis and Michael Azoff introduction © Kisaco Research. All rights reserved. Unauthorized reproduction prohibited. 3 backpropagation was invented and created a startup selling his Prognostica Microsoft Excel add-in for time series forecasting and wrote a book on the topic for publisher John Wiley & Sons in 1994.

Since 2003 Michael has worked as an IT industry analyst covering software engineering topics, from agile and DevOps, to application lifecycle management and cloud native computing. He started covering machine learning when deep learning emerged as the most recent wave of interest in AI and left his position as Distinguished Analyst at Ovum/Informa to join Kisaco Research and help build an analyst capability within the company.

My analyst coverage areas at KR Analysis

My first research project at KR was to create the first analyst comparison chart for AI chips. We invited AI chip producers to participate and were fortunate to have 16 vendors participate from across the globe: USA, UK, France, and China, and a mix of established players (Nvidia, Imagination, Intel, and Xilinx, to startups.

Our analysis showed that the market naturally fell into three areas of hot activity:

▪ Data centers and high-performance computing environments (HPC): here large boxes are installed and the aim is to achieve maximum performance for training and inferencing AI systems. The buyers are cloud hyperscalars, national research labs and agencies, and some large enterprises with big investments in AI.

▪ Small edge: the opposite end of the spectrum, building the smallest useful chip possible to sell as cheap as possible and embed in edge devices. AI is inferencing here.

▪ Automotive: an active industry in AI but highly regulated creating hurdles and technology adoption cadences that can be challenging for suppliers. AI is mainly inferencing here (for systems installed in vehicles).

We produced four Kisaco Leadership Charts out of this research.

We are also researching the machine learning (ML) software tools space, and our first report here is ML Lifecycle Solutions. The biggest challenge for enterprises is taking the research AI systems developed by their data scientist and deploying these into production at scale. Using a host of open source tools to achieve this is possible but time consuming to build and maintain, as well as prone to breakdown. This is why the ML lifecycle solution space exists.

Finally, in our first batch of KR Analysis reports we produced the KLC on engineering application lifecycle management (ALM) solutions. While ALM has been in existence as a distinct practice since KR Analysis and Michael Azoff introduction © Kisaco Research. All rights reserved. Unauthorized reproduction prohibited. 4 around 2003, it continues to evolve. We found the engineering and highly regulated industries relying on engineering and compliance oriented ALM to help manage risk and complexity.

 

Bryan Catanzaro

VP, Applied Deep Learning Research
NVIDIA

Bryan Catanzaro is vice president of Applied Deep Learning Research at NVIDIA, where he leads a team finding new ways to use AI to improve projects ranging from language understanding to computer graphics and chip design. Bryan's research at NVIDIA led to the creation of CUDNN, and more recently, he helped lead the team that invented DLSS 2.0. Prior to NVIDIA, he worked at Baidu to create next-generation systems for training and deploying end-to-end, deep learning-based speech recognition.

Bryan Catanzaro

VP, Applied Deep Learning Research
NVIDIA

Bryan Catanzaro

VP, Applied Deep Learning Research
NVIDIA

Bryan Catanzaro is vice president of Applied Deep Learning Research at NVIDIA, where he leads a team finding new ways to use AI to improve projects ranging from language understanding to computer graphics and chip design. Bryan's research at NVIDIA led to the creation of CUDNN, and more recently, he helped lead the team that invented DLSS 2.0. Prior to NVIDIA, he worked at Baidu to create next-generation systems for training and deploying end-to-end, deep learning-based speech recognition. Bryan received his PhD in Electrical Engineering and Computer Sciences from the University of California, Berkeley.

 

Dieter Ernst

Senior Fellow
Centre for International Governance Innovation

Dieter Ernst is a senior fellow at CIGI, where he explores unresolved challenges for the global governance of trade, intellectual property (IP) and innovation, addressing two main issues: finding out what adjustments are needed in the development and use of IP, in particular, patents and trade secrets, to cope with the requirements of increasingly complex and diverse global corporate networks of production and innovation; and dealing with the effects of the proliferation of strategic patenting behaviour on the organization and governance of these global networks.

Dieter Ernst

Senior Fellow
Centre for International Governance Innovation

Dieter Ernst

Senior Fellow
Centre for International Governance Innovation

Dieter Ernst is a senior fellow at CIGI, where he explores unresolved challenges for the global governance of trade, intellectual property (IP) and innovation, addressing two main issues: finding out what adjustments are needed in the development and use of IP, in particular, patents and trade secrets, to cope with the requirements of increasingly complex and diverse global corporate networks of production and innovation; and dealing with the effects of the proliferation of strategic patenting behaviour on the organization and governance of these global networks.

Based in Hawaii, he is currently a senior fellow at the East-West Center. Previously, he served as a member of the US National Academies’ Committee on Global Approaches to Advanced Computing, as a senior adviser to the Organisation for Economic Co-operation and Development in Paris, and as a research director of the Berkeley Roundtable on the International Economy at the University of California at Berkeley.

Previously, Dieter was a professor of international business at the Copenhagen Business School and served as a scientific adviser to governments, private companies and international institutions, including the World Bank, the UN Conference on Trade and Development and the UN Industrial Development Organization.

He holds a Ph.D. in economics from the University of Bremen.

 

 

Dima Rekesh

Senior Distinguished Engineer
Optum Tech

Dima Rekesh

Senior Distinguished Engineer
Optum Tech

Dima Rekesh

Senior Distinguished Engineer
Optum Tech
 

Vivenne Sze

Associate Professor
MIT

Vivenne Sze

Associate Professor
MIT

Vivenne Sze

Associate Professor
MIT
 

Priyanka Raina

Assistant Professor
Stanford

Priyanka Raina

Assistant Professor
Stanford

Priyanka Raina

Assistant Professor
Stanford
 

Shahin Farshschi

Partner
Lux Capital

Shahin empowers entrepreneurs aiming to accelerate humanity towards a brighter future through feats of engineering. He is passionate about artificial intelligence, robots, space, cars, and engines—pretty much anything you might find in an episode of Star Trek.

Shahin Farshschi

Partner
Lux Capital

Shahin Farshschi

Partner
Lux Capital

Shahin empowers entrepreneurs aiming to accelerate humanity towards a brighter future through feats of engineering. He is passionate about artificial intelligence, robots, space, cars, and engines—pretty much anything you might find in an episode of Star Trek.

He led Lux’s investments in Silicon Clocks (NASDAQ:SLAB), which shrank electronics by baking bulky quartz crystals into silicon chips; SiBeam (NASDAQ:SIMG), which aims to eliminate wires from living rooms by introducing full-HD wireless connectivity; Planet, which is launching the world’s largest fleet of Earth-imaging satellites; Plethora, which is rolling out a fleet of robotic machine shops; Flex Logix, making chips that can reprogram themselves; Nervana (NASDAQ:INTC), the first full-stack platform for machine intelligence; Mythic, bringing powerful AI to miniature, inexpensive devices; Astranis, which is building low-cost telecommunications satellites; Embodied Intelligence, which empowers industrials to perceive and act like humans; Aeva, a new sensing paradigm for autonomous machines; Arraiy, a platform for automating visual effects; SubSpace, a company providing real-time, latency-free internet; and Scaled Inference.

Previously, Shahin co-founded Vista Integrated Systems, which built wireless vital sign monitors based on a neural interface technology he developed during his PhD at UCLA. Shahin also developed hybrid electric vehicles for GM in Detroit, worked as a software developer in several Silicon Valley startups, and researched new techniques for semiconductor manufacturing. He earned his Bachelor’s in EECS at UC Berkeley.

 

Tatiana Shpeisman

Senior Engineering Manager
Google

Tatiana Shpeisman

Senior Engineering Manager
Google

Tatiana Shpeisman

Senior Engineering Manager
Google
 

Steven Woo

Rambus Fellow and Distinguished Inventor
Rambus

Steven Woo

Rambus Fellow and Distinguished Inventor
Rambus

Steven Woo

Rambus Fellow and Distinguished Inventor
Rambus
 

Igor Carron

Co-Founder & CEO
LightOn

Igor has held several positions in business development and the management of technical teams in space and nuclear engineering projects. He is also the co-organizer of the Paris Machine Learning meetup, one of the largest Data Science meetups in the world with more than 7,000 members. Igor also writes a technical blog with a focus on algorithms, data and sensors that has been viewed more than 7 million times since its inception. Igor holds a Ph.D from Texas A&M University and an Engineering degree from INPG.

Igor Carron

Co-Founder & CEO
LightOn

Igor Carron

Co-Founder & CEO
LightOn

Igor has held several positions in business development and the management of technical teams in space and nuclear engineering projects. He is also the co-organizer of the Paris Machine Learning meetup, one of the largest Data Science meetups in the world with more than 7,000 members. Igor also writes a technical blog with a focus on algorithms, data and sensors that has been viewed more than 7 million times since its inception. Igor holds a Ph.D from Texas A&M University and an Engineering degree from INPG.

 

Luis Ceze

Co-founder and CEO
OctoML

Luis Ceze is Co-founder and CEO at OctoML, Professor in the Paul G. Allen School of Computer Science and Engineering at the University of Washington, and Venture Partner at Madrona Venture Group. His research focuses on the intersection between computer architecture, programming languages, machine learning and biology. His current focus is on approximate computing for efficient machine learning andDNA-based data storage. He co-directs the Molecular Information Systems Lab (MISL), the Systems and Architectures for Machine Learning lab (SAMPL) and the Sampa Lab for HW/SW co-design.

Luis Ceze

Co-founder and CEO
OctoML

Luis Ceze

Co-founder and CEO
OctoML

Luis Ceze is Co-founder and CEO at OctoML, Professor in the Paul G. Allen School of Computer Science and Engineering at the University of Washington, and Venture Partner at Madrona Venture Group. His research focuses on the intersection between computer architecture, programming languages, machine learning and biology. His current focus is on approximate computing for efficient machine learning andDNA-based data storage. He co-directs the Molecular Information Systems Lab (MISL), the Systems and Architectures for Machine Learning lab (SAMPL) and the Sampa Lab for HW/SW co-design. He is a recipient of an NSF CAREER Award, a Sloan Research Fellowship, a Microsoft Research Faculty Fellowship, the IEEE TCCA young Computer Architect Award and UIUC Distinguished Alumni Award.

 

Igor Arsovski

CTO, ASIC Business Unit
Marvell

Igor Arsovski is the Chief Technical Officer in the ASIC Business Unit at Marvell.

He started with IBM Microelectronics in 2003 and has since worked at multiple companies across the full semiconductor vertical stack from Design Technology Co-Optimization(DTCO) of Memory & Standard Cells to full Architecture and PPA optimization of the highest performing Networking and Machine Learning ASICs.

He is currently responsible for Data Center and Automotive ASICs, defining IP, Methodology, and Packaging strategy for the next generation compute solutions.

Igor Arsovski

CTO, ASIC Business Unit
Marvell

Igor Arsovski

CTO, ASIC Business Unit
Marvell

Igor Arsovski is the Chief Technical Officer in the ASIC Business Unit at Marvell.

He started with IBM Microelectronics in 2003 and has since worked at multiple companies across the full semiconductor vertical stack from Design Technology Co-Optimization(DTCO) of Memory & Standard Cells to full Architecture and PPA optimization of the highest performing Networking and Machine Learning ASICs.

He is currently responsible for Data Center and Automotive ASICs, defining IP, Methodology, and Packaging strategy for the next generation compute solutions.

His extended focus is energy efficient building blocks for Machine Learning, Modularity, 3D Memory Integration, and Artificial Intelligence Assistants for Chip Design.

Igor has authored more than 20 IEEE papers, has over 85 patents, and is serving on multiple conference committees.

 

Charles McFarlane

Chief Business Officer
Codeplay

Charles Macfarlane is CBO and Director at Codeplay Software in Edinburgh since 2014 responsible for sales, marketing and business development. Charles graduated from Glasgow University with an honours degree in Electronic Systems and Microprocessor Engineering. Charles then followed a career doing ASIC chip design in GEC Plessey Semiconductors and Pioneer, applications engineering and marketing with VLSI/Philips/NXP in South France, and product marketing director with Broadcom® in Cambridge for mobile multimedia solutions used by Nokia®, Samsung® and Raspberry Pi®.

Charles McFarlane

Chief Business Officer
Codeplay

Charles McFarlane

Chief Business Officer
Codeplay

Charles Macfarlane is CBO and Director at Codeplay Software in Edinburgh since 2014 responsible for sales, marketing and business development. Charles graduated from Glasgow University with an honours degree in Electronic Systems and Microprocessor Engineering. Charles then followed a career doing ASIC chip design in GEC Plessey Semiconductors and Pioneer, applications engineering and marketing with VLSI/Philips/NXP in South France, and product marketing director with Broadcom® in Cambridge for mobile multimedia solutions used by Nokia®, Samsung® and Raspberry Pi®.

 

Mike Henry

Co-Founder & CEO
Mythic

Mike Henry

Co-Founder & CEO
Mythic

Mike Henry

Co-Founder & CEO
Mythic
 

Jonathan Ross

Co-Founder & CEO
Groq

Jonathan Ross is Groq’s technical founder and CEO. Prior to founding Groq he began what became Google’s TPU effort as a 20% project where he designed and implemented the core elements of the original chip. Jonathan next joined Google X’s Rapid Eval Team, the initial stage of the famed “Moonshots factory”, where he devised and incubated new Bets (Units) for Google’s parent company, Alphabet. Jonathan studied mathematics and computer science at NYU’s Courant Institute, and in his second year was the first Computer Science undergraduate to complete courses restricted to PhD students.

Jonathan Ross

Co-Founder & CEO
Groq

Jonathan Ross

Co-Founder & CEO
Groq

Jonathan Ross is Groq’s technical founder and CEO. Prior to founding Groq he began what became Google’s TPU effort as a 20% project where he designed and implemented the core elements of the original chip. Jonathan next joined Google X’s Rapid Eval Team, the initial stage of the famed “Moonshots factory”, where he devised and incubated new Bets (Units) for Google’s parent company, Alphabet. Jonathan studied mathematics and computer science at NYU’s Courant Institute, and in his second year was the first Computer Science undergraduate to complete courses restricted to PhD students.

 

Satrajit Chatterjee

Engineering Manager & ML Researcher
Google

Sat is an Engineering Manager and Machine Learning Researcher at Google AI. His current research focuses on fundamental questions in deep learning (such as understanding why neural networks generalize at all) and on applications of ML to hardware design and verification (specifically hardware for ML acceleration).

Satrajit Chatterjee

Engineering Manager & ML Researcher
Google

Satrajit Chatterjee

Engineering Manager & ML Researcher
Google

Sat is an Engineering Manager and Machine Learning Researcher at Google AI. His current research focuses on fundamental questions in deep learning (such as understanding why neural networks generalize at all) and on applications of ML to hardware design and verification (specifically hardware for ML acceleration).

Before Google, he was a Senior Vice President at Two Sigma, a leading quantitative investment manager, where he founded one of the first successful deep learning-based alpha research groups on Wall Street and led a team that built one of the earliest end-to-end FPGA-based trading systems for general purpose ultra-low latency trading. Prior to that, he was a Research Scientist at Intel where he worked on microarchitectural performance analysis and formal verification for on-chip networks. 

He did his undergraduate studies at IIT Bombay, has a PhD in Computer Science from UC Berkeley, and has published in the top machine learning, design automation, and formal verification conferences.

 

 

Dr. Chris Eliasmith

Co-Founder Co-CEO
Applied Brain Research

Dr. Chris Eliasmith

Co-Founder Co-CEO
Applied Brain Research

Dr. Chris Eliasmith

Co-Founder Co-CEO
Applied Brain Research
 

Anand Iyer

Director, Pathfinding & Product Planning
Samsung

Anand Iyer

Director, Pathfinding & Product Planning
Samsung

Anand Iyer

Director, Pathfinding & Product Planning
Samsung
 

Arun Venkatachar

VP, AI & Central Engineering
Synopsys

Arun Venkatachar

VP, AI & Central Engineering
Synopsys

Arun Venkatachar

VP, AI & Central Engineering
Synopsys
 

Buvna Ayyagari-Sangamalli

VP, Head of Design Technology
Applied Materials

Buvna Ayyagari-Sangamalli heads the Design Technology team at Applied Materials. With a career in various roles from Design Engineering to development of Customer IP Subsystems, she is intimately familiar with design challenges. At Synopsys she played a pivotal role in growing the IP business, where she led the IP Applications Engineering team and launched Customer IP Subsystems for AI, Automotive, IoT and other segments. Prior to that, she played a critical role in defining low-power EDA design methodologies. At Intel she worked on various mobile, desktop and processor chips.

Buvna Ayyagari-Sangamalli

VP, Head of Design Technology
Applied Materials

Buvna Ayyagari-Sangamalli

VP, Head of Design Technology
Applied Materials

Buvna Ayyagari-Sangamalli heads the Design Technology team at Applied Materials. With a career in various roles from Design Engineering to development of Customer IP Subsystems, she is intimately familiar with design challenges. At Synopsys she played a pivotal role in growing the IP business, where she led the IP Applications Engineering team and launched Customer IP Subsystems for AI, Automotive, IoT and other segments. Prior to that, she played a critical role in defining low-power EDA design methodologies. At Intel she worked on various mobile, desktop and processor chips. Her well-rounded 20 years in the semiconductor industry straddled architecture, design, EDA and IP.

 

 

Craig Orr

Head of US Marketing, Samsung Foundry
Samsung

Craig Orr

Head of US Marketing, Samsung Foundry
Samsung

Craig Orr

Head of US Marketing, Samsung Foundry
Samsung
 

Fadi Aboud

Senior Principal Engineer
Intel

Fadi Aboud is a Sr. Principal Engineer at Intel Corporation. He leads the development and deployment of Tools, Flows and Methodology solutions for IP, SOC and Platform level power, performance and thermal. Fadi previously led the development and deployment of Intel’s custom design implementation flow, for the high-speed core IP design.

Fadi holds a degree in electrical engineering from the Technion Institute of Haifa-Israel, graduating in 1992. He currently lives in the city of Nazareth in Israel with his wife and three children.

 

Fadi Aboud

Senior Principal Engineer
Intel

Fadi Aboud

Senior Principal Engineer
Intel

Fadi Aboud is a Sr. Principal Engineer at Intel Corporation. He leads the development and deployment of Tools, Flows and Methodology solutions for IP, SOC and Platform level power, performance and thermal. Fadi previously led the development and deployment of Intel’s custom design implementation flow, for the high-speed core IP design.

Fadi holds a degree in electrical engineering from the Technion Institute of Haifa-Israel, graduating in 1992. He currently lives in the city of Nazareth in Israel with his wife and three children.

 

 

Kim Hazelwood

Westcoast Head of Engineering, AI Research
Facebook

Kim Hazelwood is an engineering leader whose expertise lies at the intersection of scalable computer systems and applied machine learning. Her roles at Facebook have included multiple engineering organizational leadership roles across Infrastructure and Research. Prior to Facebook, Kim held positions including Director of Research at Yahoo Labs, Software Engineer in the datacenter division of Google, Research Scientist at Intel, and tenured Associate Professor of Computer Science at the University of Virginia.

Kim Hazelwood

Westcoast Head of Engineering, AI Research
Facebook

Kim Hazelwood

Westcoast Head of Engineering, AI Research
Facebook

Kim Hazelwood is an engineering leader whose expertise lies at the intersection of scalable computer systems and applied machine learning. Her roles at Facebook have included multiple engineering organizational leadership roles across Infrastructure and Research. Prior to Facebook, Kim held positions including Director of Research at Yahoo Labs, Software Engineer in the datacenter division of Google, Research Scientist at Intel, and tenured Associate Professor of Computer Science at the University of Virginia. Kim holds a PhD in Computer Science from Harvard University and has authored over 50 publications and one book. She is a recipient of the MIT "Top 35 Innovators under 35"​ award, the ACM SIGPLAN "Test of Time" Award, the Anita Borg Early Career Award, and an NSF Career Award. She currently serves on the Board of Directors for the Computing Research Association. 

 

Paolo Faraboschi

VP & HPE Fellow, AI Lab, Hewlett Packard Labs
HPE

Paolo Faraboschi leads research in the Systems Research Lab at HP Labs. His technical interests lie at the intersection of hardware and software and include low power servers and systems-on-a-chip, workload-optimized, highly-parallel and distributed systems, ILP and VLIW processor architectures, compilers, and embedded systems. Faraboschi’s current research focuses on next-generation data-centric systems.

Paolo Faraboschi

VP & HPE Fellow, AI Lab, Hewlett Packard Labs
HPE

Paolo Faraboschi

VP & HPE Fellow, AI Lab, Hewlett Packard Labs
HPE

Paolo Faraboschi leads research in the Systems Research Lab at HP Labs. His technical interests lie at the intersection of hardware and software and include low power servers and systems-on-a-chip, workload-optimized, highly-parallel and distributed systems, ILP and VLIW processor architectures, compilers, and embedded systems. Faraboschi’s current research focuses on next-generation data-centric systems. His work on system-level integration for low energy servers and scale-out architectures is a key element of the HP Moonshot System, HP’s new class of software-defined servers built to address the energy efficiency challenges of hyperscale datacenters.

 

 Previously, Faraboschi led HP Labs research in system-level modeling and simulation, an effort that resulted in the COTSon open-source simulation platform. He is also the founder of HP’s Barcelona Research Office, which pioneered research in contentprocessing systems.. Before that, Faraboschi was technical lead for the Custom-Fit Processors Project at HP Labs, Cambridge (MA), building highly-optimized, softwaredefined CPU cores. In that role, he was the principal architect of the instruction set architecture for the Lx/ST200 family of VLIW embedded processor cores (developed with STMicroelectronics) which have been used for over a decade in a variety of audio, video, and imaging consumer products, including HP's printers and scanners.

 

 A regular keynote speaker at conferences and industry events, Faraboschi is an IEEE Fellow for "contributions to embedded processor architecture & system-on-chip technology." An active member of the computer architecture community, he also serves regularly on IEEE program and organizational committees, was guest editor of the 2012 edition of IEEE Micro TopPicks, and is co-author (with Josh Fisher and Cliff Young) of the book, “Embedded Computing: a VLIW Approach to Architecture, Compilers and Tools.” A co-holder of 24 granted patents, several other patent applications, and co-author of over 65 scientific publications, Faraboschi received his M.S. and Ph.D. (Dottora

 

Rick Stevens

Assoc. Lab Director, Computing, Environment & Life Sciences
Argonne National Lab

Rick Stevens is Argonne’s Associate Laboratory Director for Computing, Environment and Life Sciences.

Rick Stevens

Assoc. Lab Director, Computing, Environment & Life Sciences
Argonne National Lab

Rick Stevens

Assoc. Lab Director, Computing, Environment & Life Sciences
Argonne National Lab

Rick Stevens is Argonne’s Associate Laboratory Director for Computing, Environment and Life Sciences.

Stevens has been at Argonne since 1982, and has served as director of the Mathematics and Computer Science Division and also as Acting Associate Laboratory Director for Physical, Biological and Computing Sciences. He is currently leader of Argonne’s Exascale Computing Initiative, and a Professor of Computer Science at the University of Chicago Physical Sciences Collegiate Division. From 2000-2004, Stevens served as Director of the National Science Foundation’s TeraGrid Project and from 1997-2001 as Chief Architect for the National Computational Science Alliance.

Stevens is interested in the development of innovative tools and techniques that enable computational scientists to solve important large-scale problems effectively on advanced scientific computers. Specifically, his research focuses on three principal areas: advanced collaboration and visualization environments, high-performance computer architectures (including Grids) and computational problems in the life sciences. In addition to his research work, Stevens teaches courses on computer architecture, collaboration technology, virtual reality, parallel computing and computational science.

 

 

Tien Shiah

Senior Manager, Marketing
Samsung

Tien Shiah is Senior Manager, Marketing for High Bandwidth Memory at Samsung Semiconductor Inc.  In this capacity, he serves as the company’s product consultant, market expert, and evangelist for HBM in the Americas, focused on providing a clear understanding of the tremendous benefits offered by HBM in the enterprise and client marketplaces. He brings more than 16 years of product marketing experience from the semiconductor and storage industries, and has presented at a number of industry conferences, such as Flash Memory Summit, the Storage Developer Conference, and Dell EMC World.

Tien Shiah

Senior Manager, Marketing
Samsung

Tien Shiah

Senior Manager, Marketing
Samsung

Tien Shiah is Senior Manager, Marketing for High Bandwidth Memory at Samsung Semiconductor Inc.  In this capacity, he serves as the company’s product consultant, market expert, and evangelist for HBM in the Americas, focused on providing a clear understanding of the tremendous benefits offered by HBM in the enterprise and client marketplaces. He brings more than 16 years of product marketing experience from the semiconductor and storage industries, and has presented at a number of industry conferences, such as Flash Memory Summit, the Storage Developer Conference, and Dell EMC World. He holds an MBA from McGill University (Montreal, Canada), and an Electrical Engineering degree from the University of British Columbia.

 

Ziad Asghar

Vice President, Snapdragon Roadmap Planning and AI, XR & Competitive Strategy
Qualcomm

Ziad Asghar

Vice President, Snapdragon Roadmap Planning and AI, XR & Competitive Strategy
Qualcomm

Ziad Asghar

Vice President, Snapdragon Roadmap Planning and AI, XR & Competitive Strategy
Qualcomm
 

Amir Eyal

CEO
Deep AI

Amir Eyal

CEO
Deep AI

Amir Eyal

CEO
Deep AI
 

Robert Ober

Chief Platform Architect, Datacenter Products
NVIDIA

Robert Ober

Chief Platform Architect, Datacenter Products
NVIDIA

Robert Ober

Chief Platform Architect, Datacenter Products
NVIDIA
 

Andrew Richards

Founder & CEO
Codeplay

Andrew Richards

Founder & CEO
Codeplay

Andrew Richards

Founder & CEO
Codeplay

AUDIENCE BREAKDOWN

AI Hardware Summit Audience Breakdown

Past attendees include: 

Platinum Partners

Gold Partners

Event Partners

Showcase Partner

Headline Media Partner

Media Partners

Become a Sponsor

Kisaco Research provides the much-needed platform on which industry executives can network, connect and learn from each other as well as meet potential industry partners.

Far from the typical ‘meet-and-greet’ exhibition experience, you – as a sponsor or exhibitor – will be positioned as a partner of the event with a focus on the benefits of your product and brand, rather than just a name on an exhibition list.

With our extensive marketing experience and strategy, your partnership with Kisaco Research will grant you a sponsorship package that is an extension and enhancement of your current marketing and branding efforts. We value your ROI and will work with you directly on your specific goals and targets – that’s why we take special care in finding the most relevant end-users to attend, so that your financial and resource investment is smartly allocated.

Find out more by calling us at +44 (0)20 3696 2920 or email us at [email protected].

Interested in a media partner pass?

This year we have a very limited number of press passes available to attend the event. If you regularly cover the AI chip industry and want to stay at the cusp of innovation and hear the latest product and company launches, get in touch. 

Contact: Finola McMahon, Marketing Director
fm@kisacoresearch.com 

Highlights

 

   highlights_2019.png

 image_collage_aihw.jpg

TESTIMONIALS

testimonials.png

The Virtual Experience

Top 10 benefits

- Tailor Your Agenda 

- More Audience Participation

- Improved Audience Visibility 

- On-Demand Content

- High Quality Speakers 

- More Networking Opportunities 

- Save Time & Money 

- Increased Content 

- More insights 

- Business Development Opportunities - Talk to our team to find out out more [email protected].

Platform Preview

The Agenda

Please complete your details to receive a copy of the 2020 agenda to explore the type of topics that will be covered. 

Watch video highligts from the AI Hardware Summit 2019: 

Download 2020 Virtual Agenda

Conference Packages

Sending Your Team? Group Discounts Available!

Applicable for Primary Market, Service Provider and Industry Rates Only. Not available for Academic or ‘Start-Up’ rates

Book a Team of 3+ - Save an Additional 10% Off
Book a Team of 5+ - Save an Additional 15% Off

If you would like to register a team of 3 or more, please email [email protected] for your discount coupon code before registering. PLEASE NOTE: Discounts cannot be combined with Early Bird Pricing or any other discount or offer. If you have any questions about your registration, please call us on +44 (0)20 3696 2920

We accept the following cards through Stripe:

Registration ends in

Saturday, August 1, 2020 to Wednesday, October 7, 2020
4 Day Pass
$749
This pass will give you access to all live content, 1-2-1 meetings and on-demand content across the 4 day event.
You will also have the ability to book 1-2-1 meetings throughout the 2 weeks that the event is taking place.
To increase your brand presence, contact Ben Edwards, [email protected]
Wednesday, May 13, 2020 to Wednesday, October 7, 2020
On-demand Pass
$249
This pass will give you access to all content on-demand after the event has taken place.
Please note, this pass will not give you access to live content or 1-2-1 meetings.
Preparing registration...

About Kisaco Research

Kisaco Research produces, designs and hosts B2B industry conferences, exhibitions and communities – focused on a specialized selection of topic areas.

Meet industry peers that will help build a career-changing network for life.

Learn from the mistakes of your peers as much as their successes—ambitious industry stalwarts who are happy to share not just what has made them successful so far but also their plans for future proofing their companies.

Note down the inspired insight that will form the foundation for future strategies and roadmaps, both at our events and through our online communities.

Invest both in your company growth and your own personal development by signing up to one of our events and get started.

Other events you might be interested in:

AI Hardware Summit Europe

Edge AI Summit 2020